1. Field of the Invention
The present invention relates to a plasma display apparatus.
2. Description of the Related Background Art
Recently, with the increase in the screen size of display apparatuses, there is an increased demand for of thin shape display apparatuses. Various kinds of thin display devices have been put into practical use, among which much attention is being paid to AC (Alternating Current) type plasma display panels as one type of such thin display device.
FIG. 1 is a schematic diagram showing the configuration of a plasma display apparatus comprising such a plasma display panel and a driver to drive this display panel.
In FIG. 1, the plasma display panel PDP 10 comprises m column electrodes D1-Dm as data electrodes, and n row electrodes X1-Xn and n row electrodes Y1-Yn which intersect each of the column electrodes. One pair of X1 (1xe2x89xa6ixe2x89xa6n) and Yi (1xe2x89xa6ixe2x89xa6n) of the row electrodes X1-Xn and Y1-Yn forms one display line of the PDP 10. The column electrodes D and the row electrodes X and Y are arranged to face each other through a discharge space filled with a discharge gas. A discharge cell corresponding to one picture element is formed at the intersection of each row electrode and each column electrode with the discharge space between them.
Each discharge cell emits light by the discharge effect, so each cell can have only two states, a xe2x80x9clight emittingxe2x80x9d state or a xe2x80x9cnon-light emittingxe2x80x9d state. That is, each discharge cell exhibits only two gradation levels, minimum brightness (non-light emitting state) and maximum brightness (light emitting state).
Therefore, the driver 100 performs gradation drive by using the subfield method in order to display brightness of half tone corresponding to a video signal supplied to the PDP 10. In the subfield method, the input video signal is converted to, for example, 4-bit picture element data corresponding to each picture element. In this drive method, the display period of one field is formed with four subfields SF1-SF4 as shown in FIG. 2, each subfield corresponding to each bit digit of such picture element data. As indicated in FIG. 2, a light emitting frequency (or light emitting period) corresponding to the weight of the subfield is allocated to each subfield.
FIG. 3 shows various kinds of driving pulses to be supplied by the driver 100 to the row electrode pairs and the column electrodes of the PDP 10 in each subfield shown in FIG. 2, and such pulse supply timing.
During the simultaneous reset process Rc shown in FIG. 3, the driver 100 first supplies positive reset pulses RPX to the row electrodes X1-Xn, and negative reset pulses RPY to the row electrodes Y1-Yn. In response to the supply of these reset pulses RPX and RPY, all the discharge cells of the PDP 10 are reset and discharged and a predetermined wall charge is uniformly formed in each discharge cell. Immediately after that, the driver 100 supplies erasing pulses EP to all the row electrodes X1-Xn of the PDP 10 at the same time. Because of the supply of such erasing pulses EP, an erasing discharge is generated in all the discharge cells and the above-mentioned wall charge disappears. Thus, all the discharge cells in the PDP 10 are initialized to the xe2x80x9cnon-light emitting cellxe2x80x9d state.
During the next picture element data write process Wc, the driver 100 first converts an input video signal into 4-bit picture element data of each picture element. Then, for example, in the subfield SF1, the driver 100 generates picture element data pulses having a voltage corresponding to the logical level of the first bit of the picture element data. Then, the driver 100 supplies such pulses to the column electrodes D1-Dm sequentially, one row at a time (picture element data pulse group DP1-DPn). For example, the driver 100 generates picture element data pulses of high voltage when the logical level of the first bit of the picture element data is xe2x80x9c1xe2x80x9d, and generates picture element data pulses of low voltage (0 volt) when the logical level is xe2x80x9c0xe2x80x9d. In addition, the driver 100 generates scanning pulses SP synchronized with the supply timing of each picture element data pulse group DP, then supplies such pulses to the row electrodes Y1-Yn sequentially. In this case, a write discharge is selectively generated and a wall charge is formed only at a discharge cell at the intersection of a display line to which scanning pulses SP are supplied and a xe2x80x9ccolumnxe2x80x9d to which high voltage picture element data pulses are supplied. Therefore, a discharge cell which has been initialized to the xe2x80x9cnon-light emitting cellxe2x80x9d state during the simultaneous reset process Rc is set to the xe2x80x9clight emitting cellxe2x80x9d state. On the other hand, a discharge cell to which the scanning pulses SP were supplied and at the same time the low voltage picture element data pulses were also supplied does not generate a write discharge. Thus, this discharge cell is maintained at the state initialized during the simultaneous reset process Rc, namely, at the xe2x80x9cnon-light emitting cellxe2x80x9d state.
During the next light emission maintaining process Ic, the driver 100 supplies maintaining pulses IPX and IPY as shown in FIG. 3 to the row electrodes X1-Xn and the row electrodes Y1-Yn alternately and repeatedly. When the supply frequency during the light emission maintaining process Ic of the subfield SF1 is xe2x80x9c1xe2x80x9d, the supply frequency (or the supply period) of the maintaining pulses IPX and IPY during the light emission maintaining process Ic of each subfield SF1-SF4 shown in FIG. 2 is as follows.
SF1: 1
SF2: 2
SF3: 4
SF4: 8
In this case, each time these maintaining pulses IPX and IPY are supplied, only a discharge cell having a wall charge remaining in its discharge space, namely, a xe2x80x9clight emitting cellxe2x80x9d discharges (hereinafter called maintenance discharge). That is, only a discharge cell which was set to be a xe2x80x9clight emitting cellxe2x80x9d during said picture element data write process Wc emits light accompanied by said maintenance discharge repeatedly by a frequency allocated to each subfield as described above, and maintains its light emitting state.
During the next erasing process E, the driver 100 supplies erasing pulses EP as shown in FIG. 3 to the row electrodes Y1-Yn at the same time. By the supply of such erasing pulses EP, all the discharge cells of the PDP 10 perform erasing discharge, and the wall charge remaining in such discharge cell disappears.
By the above-mentioned driving, a write discharge is selectively generated in each discharge cell in accordance with the input video signal. Only a discharge cell in which said write discharge was generated repeats light emission due to maintenance discharge by a frequency allocated to such subfield. In this case, intermediate brightness corresponding to the total number of light emissions performed in each subfield during one field display period is visible.
By the above-mentioned various kinds of discharge, in the PDP 10, a discharge current flows from the driver 100 to a discharge cell to be discharged through the row electrodes. In this case, a voltage drop occurs in the driving pulses supplied to the row electrodes because of the electric resistance of the row electrodes themselves. Especially, the voltage drop of the supplied driving pulses of the discharge cell G11 on the side of the driver 100 as shown in FIG. 1 is different from that of the discharge cell G1m. In addition, if the number of discharge cells to be discharged on one display line increases, the discharge current flowing through such display line increases too. Therefore, the voltage drop of the driving pulses for the discharge cell G1m shown in FIG. 1 also increases. As a result, if the voltage of the driving pulses to be supplied to the discharge cell G1m falls below a predetermined level because of such voltage drop, a desired amount of the wall charge is no longer formed in the discharge cell G1m. As a result, when said maintenance discharge takes place, a predetermined emission brightness can not be obtained. Therefore, in this case, the emission brightness of the discharge cell G11 shown in FIG. 1 is different from that of the discharge cell G1m, resulting in an xe2x80x9cuneven brightnessxe2x80x9d in one display screen and deterioration of display quality.
The number of discharge cells to be discharged on one display line is not necessarily the same in all the subfields, so the brightness drop of each subfield is different from the others, so tone disturbance may occur.
It is an object of the present invention to solve said problems and to provide a plasma display apparatus which can display tone excellently.
A plasma display apparatus according to the present invention comprises a plasma display panel forming a discharge cell for a picture element at each intersection of a plurality of row electrodes carrying a display line and a plurality of column electrodes intersecting with said row electrodes; and a driver for forming one field display period of an input video signal with a plurality of subfields and driving the tone of said plasma display panel, said driver comprising a picture element data write driver for generating scanning pulses for causing discharge selectively for setting each of said discharge cells to a light emitting state or a non-light emitting state in response to picture element data corresponding to said input video signal, and supplying such scanning pulses to each of said row electrodes sequentially; a light emission maintenance driver for generating maintaining pulses for causing maintenance discharge for emitting said discharge cells in said light emitting cell state only repeatedly and supplying the maintaining pulses to each of said row electrodes; an impedance estimator for obtaining estimated impedance by estimating the impedance of said plasma display panel based on said picture element data; and a pulse width controller for changing the pulse width of said scanning pulses and said maintaining pulses in accordance with said estimated impedance.